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dc.contributor.author | Astrada, Juan![]() |
es_ES |
dc.contributor.author | De Angelo, Cristian![]() |
es_ES |
dc.date.accessioned | 2019-09-24T07:28:15Z | |
dc.date.available | 2019-09-24T07:28:15Z | |
dc.date.issued | 2019-09-20 | |
dc.identifier.issn | 1697-7912 | |
dc.identifier.uri | http://hdl.handle.net/10251/126282 | |
dc.description.abstract | [EN] In this paper we propose a methodology for the design of the single-phase inverter control system for UPS applications, which allows to meet the performance requirements of the international power quality standards IEC62040-3 and IEC61000-2-2. The control system consists of a conventional multi-loop with Proportional-Integral-Derivative type controllers and a multi-rate Repetitive Controller in plug-in configuration (MR-OHRC). The proposal constitutes a conventional multi-loop design methodology with which the inverter output impedance is reduced and the performance of the MR-OHRC is complemented. In this way, variations in the output voltage are attenuated as a result of disturbances caused by sudden changes in the load current and non-linear loads. This strategy also allows to overcome the limitations of dynamic response and reduce the settling time of the MR-OHRC. The validity of the proposal is analyzed considering the requirements of international power quality standards in relation to the dynamic response, individual harmonic content and harmonic distortion, in an experimental 2kVA prototype. | es_ES |
dc.description.abstract | [ES] En este trabajo se propone una metodología de diseño del sistema de control de un inversor monofásico para aplicaciones en UPS, que permite cumplir con las exigencias de desempeño de las normas internacionales de calidad de energía IEC62040-3 e IEC61000-2-2. El sistema de control consta de un multi-lazo convencional con controladores del tipo Proporcional-Integral-Derivativo y un Controlador Repetitivo en configuración plug-in con multi-rate (MR-OHRC). La propuesta constituye una metodología de diseño del multi-lazo convencional con la que se reduce la impedancia de salida del inversor y complementa el desempeño del MR-OHRC. De este modo se atenúan las variaciones en la tensión de salida como resultado de perturbaciones producidas por cambios súbitos en la corriente de carga y la alimentación de cargas no lineales. Esta estrategia permite además superar las limitaciones de respuesta dinámica y reducir el tiempo de establecimiento del MR-OHRC. La validez de la propuesta se analiza considerando las exigencias de normas internacionales de calidad de energía en relación a la respuesta dinámica, contenido armónico individual y distorsión armónica, en un prototipo experimental de 2kVA. | es_ES |
dc.description.sponsorship | El presente trabajo es financiado por la Secretaría de Ciencia y Técnica de la Universidad Nacional de Río Cuarto (SeCyT, UNRC) y el FONCyT de la Agencia Nacional de Promoción Científica y Tecnológica. | es_ES |
dc.language | Español | es_ES |
dc.publisher | Universitat Politècnica de València | |
dc.relation.ispartof | Revista Iberoamericana de Automática e Informática. | |
dc.rights | Reconocimiento - No comercial - Sin obra derivada (by-nc-nd) | es_ES |
dc.subject | Electrónica de Potencia | es_ES |
dc.subject | Inversor CC-CA | es_ES |
dc.subject | Control PID | es_ES |
dc.subject | Control Repetitivo | es_ES |
dc.subject | Power Electronics | es_ES |
dc.subject | DC-AC Inverter | es_ES |
dc.subject | PID Control | es_ES |
dc.subject | Repetitive Control | es_ES |
dc.title | Reducción de la impedancia de salida en inversores monofásicos para UPS con multi-lazo convencional y plug-in repetitivo | es_ES |
dc.title.alternative | Reduction of the output impedance in single phase inverters for UPS combining conventional multi-loop and plug-in repetitive control | es_ES |
dc.type | Artículo | es_ES |
dc.date.updated | 2019-09-24T06:57:35Z | |
dc.identifier.doi | 10.4995/riai.2019.11034 | |
dc.rights.accessRights | Abierto | es_ES |
dc.description.bibliographicCitation | Astrada, J.; De Angelo, C. (2019). Reducción de la impedancia de salida en inversores monofásicos para UPS con multi-lazo convencional y plug-in repetitivo. Revista Iberoamericana de Automática e Informática. 16(4):391-402. https://doi.org/10.4995/riai.2019.11034 | es_ES |
dc.description.accrualMethod | SWORD | es_ES |
dc.relation.publisherversion | https://doi.org/10.4995/riai.2019.11034 | es_ES |
dc.description.upvformatpinicio | 391 | es_ES |
dc.description.upvformatpfin | 402 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 16 | |
dc.description.issue | 4 | |
dc.identifier.eissn | 1697-7920 | |
dc.contributor.funder | Universidad Nacional de Río Cuarto | |
dc.contributor.funder | Agencia Nacional de Promoción Científica y Tecnológica, Argentina | |
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